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af9013/13s/13a/13as/15/15a dvb-t cofdm demodulator 12/1/08 preliminary specification features complete cofdm dvb-t demodulator single chip ic compliant with etsi en 300 744 and nordig unified 1.0.2 superior dynamic multipath performance in pre/post-echo, and long echo environments joint common phase error correction and channel estimation for low cost tuner support integrated 10-bit adc and pll dual agc (rf and if) control with 1-bit sd output fully programmable rf/if agc take-over- point (top) to work with any silicon/can- tuner digital carrier frequency offset 500khz correction digital crystal frequency jitter 100ppm compensation all-digital time and frequency synchronization tracking loop adaptive fft window position tracking in mobile/portable environments two-dimensional time-frequency channel estimation, tracking, and filtering for excellent fixed and mobile reception all-digital adjacent channel interference (aci) filter for supporting 6/7/8mhz bandwidth with a single 8mhz saw filter adaptive co-channel interference (cci) filter for pal/secam/nicam rejection configurable if sampling (high or low if) from a single crystal frequency comprehensive performance monitoring parameters available through register access embedded high-speed usb 2.0 interface compatible with usb1.1 supports usb suspend and selective suspend modes capable of entering c3 mode for notebook power-saving applications complete api c source code for easy integration with most backend host processors microsoft broadcast driver architecture ( bda ) driver support with whql/mce certified and compliant for usb applications ir (infrared) interface compliant with mce rc6 protocol is supported for remote control using hid class integrated transport stream de-multiplexer (32-entry pid filtering ) serial and parallel mpeg2-ts interface output support second mpeg2-ts input for pip/pvr applications support dual display transport stream output from mpeg-ts and usb interfaces low power consumption 56-pin qfn and 64-pin lqfp packages applications digital dvb-t set-top boxes integrated digital dvb-t televisions usb bus-powered portable dvb-t receivers for pc desktops/notebooks dvd recorders with dvb-t receivers pmc (personal multimedia center) or pvr (personal video recorder) with dvb-t receivers mobile performance doppler tolerance for qef at 8mhz with c/n=25db ( af9013/13a and af9015/15a only) 2k qpsk cr1/2 gi1/32 480hz 2k 64qam cr1/2 gi1/32 120hz 8k 16qam cr2/3 gi1/4 50hz www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary specification ver. 1.2_2007_12_19 af9013/13s/13a/13as/15/15as afa technologies confidential proprietary i revision history revision date description 0.9 3/27/2006 first draft 0.95 3/29/2006 first preliminary release 0.96 5/2/2006 editorial 1.0 6/5/2006 filled in tbd items 1.1 3/7/2007 add 9013a/9013as/9015a 1.2 12/19/2007 add model no. AF9013S-n1* 1.3 2/18/2008 remove asterisk (*) from model number s ordering information model number description package af9013-l2 dvb-t cofdm demodulator with mpeg interfa ce 64 -pin lqfp, pb-free af9013-n1 dvb-t cofdm demodulator with mpeg interfa ce 56-pin qfn, pb free AF9013S-n1 dvb-t cofdm demodulator with mpeg interf ace 56-pin qfn, pb free AF9013S-l2 dvb-t cofdm demodulator with mpeg interf ace 64-pin lqfp, pb-free af9015-n1 dvb-t cofdm demodulator with usb interfac e 56-pin qfn, pb-free af9013a-l2 dvb-t cofdm demodulator with mpeg interf ace 64 -pin lqfp, pb-free af9013a-n1 dvb-t cofdm demodulator with mpeg interf ace 56-pin qfn, pb free af9013as-l2 dvb-t cofdm demodulator with mpeg inter face 64-pin lqfp, pb-free af9015a-n1 dvb-t cofdm demodulator with usb interfa ce 56-pin qfn, pb-free unless otherwise specified, in the following contex t the description for af9013 applies for af9013a, t he description for AF9013S applies for af9013as, and d escription for af9015 applies to af9015a. www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary specification ver. 1.1_2007_03_07 af9013/13s/13a/13as/15/15as afa technologies confidential proprietary ii table of contents 1 description...................................... ................................................... ............................................6 2 block diagram .................................... ................................................... .......................................7 3 pin description.................................. ................................................... .........................................8 3.1 p in d iagrams ................................................... ................................................... ..............................8 56-pin usb mode (af9015-n1/af9015a-n1) ............ ................................................... ....................8 64-pin mpeg mode (af9013-l2/af9013a-l2) ........... ................................................... ...................9 64-pin mpeg mode (AF9013S-l2/af9013as-l2) ......... ................................................... ..............10 56-pin mpeg mode (af9013-n1/AF9013S-n1/af9013a-n1) ................................................... .....11 3.2 p in l ist ................................................... ................................................... ......................................12 3.3 d etailed p in d escriptions ................................................... ................................................... ......15 4 functional description ........................... ................................................... ............................17 4.1 o peration m odes ................................................... ................................................... .....................17 mpeg ts mode (af9013/13s only) .................... ................................................... ........................17 standard usb2.0 mode (af9015 only)................ ................................................... ........................17 concurrent mode (af9015 only)..................... ................................................... .............................18 4.2 a nalog i nterface ................................................... ................................................... .....................18 crystal oscillator................................ ................................................... ...........................................18 analog-to-digital converter (adc)................. ................................................... ...............................18 automatic gain control (agc)...................... ................................................... ................................18 4.3 cofdm d igital s ignal p rocessing ................................................... ...........................................20 initialization .................................... ................................................... ...............................................20 time-domain signal processing..................... ................................................... ..............................20 frequency-domain signal processing................ ................................................... ..........................21 synchronization loop .............................. ................................................... .....................................21 4.4 f orward e rror c orrection ................................................... ................................................... ..21 4.5 p erformance m onitoring ................................................... ................................................... .......21 4.6 2-w ire i nterface ................................................... ................................................... .....................21 host interface.................................... ................................................... ............................................22 tuner interface................................... ................................................... ...........................................22 4.7 mpeg-2 t ransport s tream i nterface ................................................... ......................................22 parallel output interface ......................... ................................................... ......................................26 serial output interface ........................... ................................................... .......................................26 serial input interface (af9015 only) .............. ................................................... ..............................27 4.8 usb i nterface (af9015 o nly ).................................................. ................................................... ..28 usb descriptors ................................... ................................................... ........................................28 usb control protocol.............................. ................................................... ......................................28 default endpoint (endpoint 0) ..................... ................................................... .............................................28 control messages .................................. ................................................... ..................................................2 8 data messages ..................................... ................................................... ................................................... 28 4.9 i nfrared (ir) i nterface (af9015 o nly ) .................................................. ......................................29 the function key and alternative keys............. ................................................... ...........................29 4.10 t he e xternal eeprom ............................................. ................................................... ...............29 4.11 b oot s cheme ................................................... ................................................... ..........................29 5 electrical characteristics ....................... ................................................... .......................30 5.1 a bsolute m aximum r atings ................................................... ................................................... .....30 5.2 dc e lectrical c haracteristics ................................................... ................................................31 5.3 a nalog c haracteristics ................................................... ................................................... .........34 www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary specification ver. 1.1_2007_03_07 af9013/13s/13a/13as/15/15as afa technologies confidential proprietary 3 5.4 ac e lectrical c haracteristics ................................................... .................................................34 mpeg-2 ts output.................................. ................................................... .....................................34 mpeg-2 ts input (af9015 only) ..................... ................................................... ............................35 2-wire bus output ................................ ................................................... .......................................36 2-wire bus input .................................. ................................................... .........................................37 6 mechanical specification......................... ................................................... ...........................38 6.1 lqfp-64 o utline d imensions ................................................... ................................................... ..38 6.2 qfn-56 o utline d imensions ................................................... ................................................... ....39 7 register list .................................... ................................................... .........................................40 www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary specification ver. 1.1_2007_03_07 af9013/13s/13a/13as/15/15as afa technologies confidential proprietary iv list of figures figure 1: block diagram of af9013/13s/15. .......... ................................................... ................7 figure 2: af9015 56-pin usb mode pin diagram. ...... ................................................... .............8 figure 3: af9013 64-pin mpeg mode pin diagram. ..... ................................................... ...........9 figure 4: AF9013S 64-pin mpeg mode pin diagram..... ................................................... ........10 figure 5: af9013 56-pin mpeg mode pin diagram. .... ................................................... ........11 figure 6: dual agc control......................... ................................................... ..........................19 figure 7: top operations for inverted (left) and no n-inverted (right) voltage- gain curves........................................ ................................................... ...........................................20 figure 8: an example of mpeg2 parallel interface ti ming diagram. ......................23 figure 9: timing diagram with continuous mpfrm in p arallel mode. .....................26 figure 10: timing diagram with gapped mpfrm in para llel mode. ............................26 figure 11: timing diagram of continuous mpfrm signa l in serial mode................27 figure 12: timing diagram of gapped mpfrm signal in serial mode. ........................27 figure 13: timing diagram of the af9015 mpeg-2 ts s erial input interface...........27 figure 14: af9013/13s/15 mpeg-2 ts output timing di agram. ...........................................34 figure 15: af9015 mpeg-2 ts input timing diagram... ................................................... .......35 figure 16: af9013/13s/15 2-wire bus output timing d iagram. .........................................36 figure 17: af9013/13s/15 2-wire bus input timing di agram. ............................................. 37 figure 18: lqfp-64 outline dimensions.............. ................................................... .................38 figure 19: qfn-56 outline dimensions............... ................................................... ..................39 www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary v list of tables table 1: af9013/13s/15 pin list.......................................... ................................................... ....... 12 table 2: digital i/o pin detailed description. ..... ................................................... ......................... 14 table 3: analog i/o pin detailed description. ...... ................................................... ....................... 15 table 4: power/ground pin detailed description. .... ................................................... ................... 15 table 5: strapping pins sampled at the rising edge of the reset signal. ............................... .... 15 table 6: af9015 operation mode selection. .......... ................................................... .................... 16 table 7: af9013/13s/15 2-wire bus address mapping table.................. ...................................... 21 table 8: af9013/13s/15 mpeg-2 ts interface pins. ......................... .......................................... 23 table 9: the af9013/13s/15 mpeg-2 ts interface mode selection. ................ .......................... 23 table 10: configurable parameters of the af9013/13s/15 mpeg-2 ts interface....................... 23 table 11: af9013/13s/15 absolute maximum ratings.......................... ........................................ 29 table 12: af9013/13s/15 dc electrical characteristics (not applicable for 9013a/13as/15a ). ... 30 table 13: af9013a/13as/15a dc electrical characteristics (not applicable for 9013/13s/15 ). ... 31 table 14: af9013/13s/15 analog electrical characteristics. ................ ........................................ 33 table 15: af9013/13s/15 mpeg-2 ts output timing............................ ....................................... 34 table 16: af9015 mpeg-2 ts input timing ............................ ................................................... .. 34 table 17: af9013/13s/15 2-wire bus output timing........................... ........................................... 35 table 18: af9013/13s/15 2-wire bus input timing........................... ............................................. 36 table 19: af9013/13s/15 register list. .................................... ................................................... .. 39 www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 6 1 description the af9013/13s/15 dvb-t cofdm demodulator is a versatile second-gene ration single-chip ic that supports multiple interfaces including serial and p arallel mpeg2-ts and embedded usb 2.0 interface wit h built-in de-multiplexer. it is compliant with both etsi en 300 744 and nordig unified 1.0.2, and it c an operate at 2k or 8k mode with 6, 7, or 8mhz bandwid th. all modulations (qpsk, 16qam, 64qam), code rates (1/2, 2/3, 3/4, 5/6, 7/8), and guard interval s (1/4, 1/8, 1/16, 1/32) are supported and automati cally detected from the tps parameters. af9013/13s/15 integrates a 10-bit analog-to-digital converter (a dc) capable of delivering the performance required for all modulations and code r ates of dvb-t. it supports direct sampling of if ( e.g. , 36.125 mhz or 43.75 mhz) or low if ( e.g. , 4.57mhz) signals. the device uses the most advanced digital signal pr ocessing techniques to combat various impairments encountered in fixed, portable, and mobile dvb-t ch annels. af9013/13s/15 provides single agc or dual rf/if agc control optio ns for maximal flexibility in tuner selections. the agc control loop bandwidth is desi gned to track a wide dynamic range of the received signal levels for slow or fast channel variations. in af9013/13s/15, an active impulse noise rejection algorithm remove s the detrimental effects of the impulse noise and significantly improves the robust ness of tv reception against interference from vehi cles and electrical appliances. co-channel interference is actively searched and re jected by a digital notch filter in af9013/13s/15 . the digital notch filter is enabled only when the inter ference is present to avoid any unnecessary signal loss. adjacent channel interference is rejected by precis ely controlled digital filters for 6, 7, and 8mhz bandwidth. this makes it possible to use a single 8mhz saw filter independent of the bandwidth used. the all-digital synchronization tracking loops of af9013/13s/15 are capable of recovering carrier frequency offsets as large as 500 khz and tolerating crystal jitters as large as 100ppm. the adaptive fft window position tracking loop in af9013/13s/15 accurately identifies pre-echo or post-echo multip ath channels even in highly mobile environments. there fore, inter-symbol interference (isi) and inter-car rier interference (ici) is greatly reduced. in af9013/13s/15 , the common phase error caused by tuner phase nois e is corrected by a joint channel estimation and phase noise tracking algorithm, thus enabling the use of low cost tuners. besides, the multi-dimensional channel estimation and tracking s cheme in af9013 and af9015 adaptively adjusts its internal parameters to reflect the different requir ements in fixed, portable, or mobile channels. hen ce, optimal performance can be achieved for all dvb-t a pplications. AF9013S , on the other hand, is optimized for performance in stationary environment s. af9013/13s/15 provides a comprehensive set of performance monitor ing parameters accessible through the 2-wire bus. these parameters include signal st rength and signal quality indicators, post-viterbi bit error rate, reed-solomon packet error rate, tps loc k and mpeg sync lock indicators, carrier and crysta l offsets, and many more. af9015 also includes a serial input interface for accepti ng a secondary mpeg2 transport stream (ts) input, thus enabling applications such as picture-i n-picture (pip) and personal video recorder (pvr). it also provides a serial interface for concurrent mpe g2 ts output, and can be easily incorporated into devices with dual display. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 7 a complete set of application programming interface (api) is available for af9013/13s/15 , facilitating fast and easy integration into products. furthermore, a complete set of microsoft bda (broadcast driver architecture) and mce compliant drivers are provide d for af9015 . together with the built-in usb and ir (infrared) interfaces, af9015 provides a complete and low cost solution for a dv b-t usb portable receiver. 2 block diagram figure 1 shows the block diagram of af9013/13s/15 dvb-t cofdm demodulator. external host if agc rf agc if in tuner agc co-channel interference filter baseband conversion and interpolator time domain impulse noise rejection adjacent channel interference filter time and frequency synchronization control channel estimator feq fec performance monitor tps decoder fft adc de- multiplexer usb interface mpeg2-ts usb 2-wire bus interface control unit figure 1: block diagram of af9013/13s/15 . www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 8 3 pin description 3.1 pin diagrams 3.1.1 56-pin usb mode ( af9015-n1 / af9015a-n1 ) 28 ir 27 vss 26 vdd 25 saddr0/gpio0 24 strapclk/gpio1 23 strap/lock1 22 pwrdw/lock2 21 mpfail 20 scl 19 sda 18 reset# 17 vssio 16 vddio 15 testmode gnda 1 xout 2 xin 3 vdda33 4 vdda18 5 clko 6 mpclk 7 mpstr 8 vdd 9 vss 10 vddio 11 vssio 12 mpfrm 13 mpdata 14 42 tunsda 41 tunscl 40 vssio 39 vddio 38 vss 37 vdd 36 usbgpiot1 35 vbus 34 xtali_usb 33 xtalo_usb 32 avddh_usb 31 agnd_usb 30 dp 29 dm rfagc 43 ifagc 44 vdd 45 vss 46 gnda 47 vdda33 48 rrefx 49 vrefp 50 vrefn 51 vip 52 vin 53 vdda33 54 gnda 55 vdda18_pll 56 56-pin usb mode 28 ir 27 vss 26 vdd 25 saddr0/gpio0 24 strapclk/gpio1 23 strap/lock1 22 pwrdw/lock2 21 mpfail 20 scl 19 sda 18 reset# 17 vssio 16 vddio 15 testmode gnda 1 xout 2 xin 3 vdda33 4 vdda18 5 clko 6 mpclk 7 mpstr 8 vdd 9 vss 10 vddio 11 vssio 12 mpfrm 13 mpdata 14 42 tunsda 41 tunscl 40 vssio 39 vddio 38 vss 37 vdd 36 usbgpiot1 35 vbus 34 xtali_usb 33 xtalo_usb 32 avddh_usb 31 agnd_usb 30 dp 29 dm rfagc 43 ifagc 44 vdd 45 vss 46 gnda 47 vdda33 48 rrefx 49 vrefp 50 vrefn 51 vip 52 vin 53 vdda33 54 gnda 55 vdda18_pll 56 56-pin usb mode 56-pin usb mode figure 2: af9015 56-pin usb mode pin diagram. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 9 3.1.2 64-pin mpeg mode ( af9013-l2 / af9013a-l2 ) 32 mpdata4 31 mpdata3 30 mpdata2 29 vss 28 vdd 27 mpdata1 26 mpdata0 25 mpfail 24 scl 23 sda 22 reset# 21 vss 20 vdd 19 vssio 18 vddio 17 testmode nc 1 nc 2 nc 3 gnda 4 xout 5 xin 6 vdda33 7 vdda18 8 saddr0/gpio0/lock4 9 strapclk/gpio1/lock3 10 vdd 11 vss 12 vddio 13 vssio 14 pwrdw/lock2 15 strap/lock1 16 48 tunsda 47 tunscl 46 vssio 45 vddio 44 vss 43 vdd 42 mpclk 41 mpstr 40 mpfrm 39 vss 38 vdd 37 mpdata7 36 mpdata6 35 mpdata5 34 vssio 33 vddio rfagc 49 ifagc 50 vdd 51 vss 52 gnda 53 vdda33 54 rrefx 55 vrefp 56 vcm 57 vrefn 58 vip 59 vin 60 vdda33 61 gnda 62 vdda18_pll 63 gnda 64 64-pin mpeg mode 32 mpdata4 31 mpdata3 30 mpdata2 29 vss 28 vdd 27 mpdata1 26 mpdata0 25 mpfail 24 scl 23 sda 22 reset# 21 vss 20 vdd 19 vssio 18 vddio 17 testmode nc 1 nc 2 nc 3 gnda 4 xout 5 xin 6 vdda33 7 vdda18 8 saddr0/gpio0/lock4 9 strapclk/gpio1/lock3 10 vdd 11 vss 12 vddio 13 vssio 14 pwrdw/lock2 15 strap/lock1 16 48 tunsda 47 tunscl 46 vssio 45 vddio 44 vss 43 vdd 42 mpclk 41 mpstr 40 mpfrm 39 vss 38 vdd 37 mpdata7 36 mpdata6 35 mpdata5 34 vssio 33 vddio rfagc 49 ifagc 50 vdd 51 vss 52 gnda 53 vdda33 54 rrefx 55 vrefp 56 vcm 57 vrefn 58 vip 59 vin 60 vdda33 61 gnda 62 vdda18_pll 63 gnda 64 64-pin mpeg mode 64-pin mpeg mode figure 3: af9013 64-pin mpeg mode pin diagram. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 10 3.1.3 64-pin mpeg mode ( AF9013S-l2 / af9013as-l2 ) 32 mpdata4 31 mpdata3 30 mpdata2 29 vss 28 vdd 27 mpdata1 26 mpdata0 25 mpfail 24 scl 23 sda 22 reset# 21 vss 20 vdd 19 vssio 18 vddio 17 testmode nc 1 nc 2 nc 3 gnda 4 xout 5 xin 6 vdda33 7 vdda18 8 saddr0/gpio0/lock4 9 strapclk/gpio1/lock3 10 vdd 11 vss 12 vddio 13 vssio 14 pwrdw/lock2 15 strap/lock1 16 48 tunsda 47 tunscl 46 vssio 45 vddio 44 vss 43 vdd 42 mpclk 41 mpstr 40 mpfrm 39 vss 38 vdd 37 mpdata7 36 mpdata6 35 mpdata5 34 vssio 33 vddio rfagc 49 ifagc 50 vdd 51 vss 52 gnda 53 vdda33 54 rrefx 55 vrefp 56 vcm 57 vrefn 58 vip 59 vin 60 vdda33 61 gnda 62 vdda18_pll 63 gnda 64 64-pin mpeg mode 32 mpdata4 31 mpdata3 30 mpdata2 29 vss 28 vdd 27 mpdata1 26 mpdata0 25 mpfail 24 scl 23 sda 22 reset# 21 vss 20 vdd 19 vssio 18 vddio 17 testmode nc 1 nc 2 nc 3 gnda 4 xout 5 xin 6 vdda33 7 vdda18 8 saddr0/gpio0/lock4 9 strapclk/gpio1/lock3 10 vdd 11 vss 12 vddio 13 vssio 14 pwrdw/lock2 15 strap/lock1 16 48 tunsda 47 tunscl 46 vssio 45 vddio 44 vss 43 vdd 42 mpclk 41 mpstr 40 mpfrm 39 vss 38 vdd 37 mpdata7 36 mpdata6 35 mpdata5 34 vssio 33 vddio rfagc 49 ifagc 50 vdd 51 vss 52 gnda 53 vdda33 54 rrefx 55 vrefp 56 vcm 57 vrefn 58 vip 59 vin 60 vdda33 61 gnda 62 vdda18_pll 63 gnda 64 64-pin mpeg mode 64-pin mpeg mode figure 4: AF9013S 64-pin mpeg mode pin diagram. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 11 3.1.4 56-pin mpeg mode ( af9013-n1 / AF9013S-n1 / af9013a-n1 ) 28 mpdata4 27 mpdata3 26 mpdata2 25 mpdata1 24 mpdata0 23 mpfail 22 scl 21 sda 20 reset# 19 vss 18 vdd 17 vssio 16 vddio 15 testmode gnda 1 xout 2 xin 3 vdda33 4 vdda18 5 saddr0/gpio0/lock4 6 strapclk/gpio1/lock3 7 ts56gpio 8 vdd 9 vss 10 vddio 11 vssio 12 pwrdw/lock2 13 strap/lock1 14 42 tunsda 41 tunscl 40 vssio 39 vddio 38 vss 37 vdd 36 mpclk 35 mpstr 34 mpfrm 33 mpdata7 32 mpdata6 31 mpdata5 30 vssio 29 vddio rfagc 43 ifagc 44 vdd 45 vss 46 gnda 47 vdda33 48 rrefx 49 vrefp 50 vrefn 51 vip 52 vin 53 vdda33 54 gnda 55 vdda18_pll 56 56-pin mpeg mode 28 mpdata4 27 mpdata3 26 mpdata2 25 mpdata1 24 mpdata0 23 mpfail 22 scl 21 sda 20 reset# 19 vss 18 vdd 17 vssio 16 vddio 15 testmode gnda 1 xout 2 xin 3 vdda33 4 vdda18 5 saddr0/gpio0/lock4 6 strapclk/gpio1/lock3 7 ts56gpio 8 vdd 9 vss 10 vddio 11 vssio 12 pwrdw/lock2 13 strap/lock1 14 42 tunsda 41 tunscl 40 vssio 39 vddio 38 vss 37 vdd 36 mpclk 35 mpstr 34 mpfrm 33 mpdata7 32 mpdata6 31 mpdata5 30 vssio 29 vddio rfagc 43 ifagc 44 vdd 45 vss 46 gnda 47 vdda33 48 rrefx 49 vrefp 50 vrefn 51 vip 52 vin 53 vdda33 54 gnda 55 vdda18_pll 56 56-pin mpeg mode 56-pin mpeg mode figure 5: af9013 56-pin mpeg mode pin diagram. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 12 3.2 pin list table 1: af9013/13s/15 pin list. pin no. af9015/15a 56-pin usb mode pin name af9013/13s/13a/13as 64-pin mpeg mode pin name af9013/13s/13a 56-pin mpeg mode pin name 1 gnda nc gnda 2 xout nc xout 3 xin nc xin 4 vdda33 gnda vdda33 5 vdda18 xout vdda18 6 clko xin saddr0/gpio0/lock4 7 mpclk vdda33 strapclk/gpio1/lock3 8 mpstr vdda18 ts56gpio 9 vdd saddr0/gpio0/lock4 vdd 10 vss strapclk/gpio1/lock3 vss 11 vddio vdd vddio 12 vssio vss vssio 13 mpfrm vddio pwrdw/lock2 14 mpdata vssio strap/lock1 15 testmode pwrdw/lock2 testmode 16 vddio strap/lock1 vddio 17 vssio testmode vssio 18 reset# vddio vdd 19 sda vssio vss 20 scl vdd reset# 21 mpfail vss sda 22 pwrdw/lock2 reset# scl 23 strap/lock1 sda mpfail 24 strapclk/gpio1 scl mpdata0 25 saddr0/gpio0 mpfail mpdata1 26 vdd mpdata0 mpdata2 27 vss mpdata1 mpdata3 28 ir vdd mpdata4 29 dm vss vddio 30 dp mpdata2 vssio 31 agnd_usb mpdata3 mpdata5 32 avddh_usb mpdata4 mpdata6 33 xtalo_usb vddio mpdata7 www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 13 34 xtali_usb vssio mpfrm 35 vbus mpdata5 mpstr 36 usbgpiot1 mpdata6 mpclk 37 vdd mpdata7 vdd 38 vss vdd vss 39 vddio vss vddio 40 vssio mpfrm vssio 41 tunscl mpstr tunscl 42 tunsda mpclk tunsda 43 rfagc vdd rfagc 44 ifagc vss ifagc 45 vdd vddio vdd 46 vss vssio vss 47 gnda tunscl gnda 48 vdda33 tunsda vdda33 49 rrefx rfagc rrefx 50 vrefp ifagc vrefp 51 vrefn vdd vrefn 52 vip vss vip 53 vin gnda vin 54 vdda33 vdda33 vdda33 55 gnda rrefx gnda 56 vdda18_pll vrefp vdda18_pll 57 vcm 58 vrefn 59 vip 60 vin 61 vdda33 62 gnda 63 vdda18_pll 64 gnda www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 14 3.3 detailed pin descriptions table 2: digital i/o pin detailed description. pin name pin description i/o type integrated pull- up/down state immediately after reset s addr0/gpio0, s addr0/gpio0/lock4 2-wire bus address strapping; or gpo pin i/o cmos pull-down low strapclk/gpio1, strapclk/gpio1/lock3 crystal frequency strapping; or gpo pin i/o cmos pull-up high pwrdw/lock2 crystal frequency strapping; power down signal; or gpio pin i/o cmos pull-up high-z strap/lock1 strap select: needs to be pulled down for normal mode; or gpio pin i/o cmos pull-down high-z ts56gpio usbgpiot1 gpio pins i/o cmos pull-down pull-up high-z testmode test mode select: needs to be pulled down for normal mode i/o cmos pull-down high-z reset# reset signal, active low i/o cmos pull-up high-z sda, scl primarily 2-wire bus i/o open drain pull-up high-z mpdata0-7 mpeg2 data bus i/o cmos none high-z mpfail mpeg2 frame uncorrectable i/o cmos none high-z mpclk mpeg2 clock i/o cmos none high-z mpfrm mpeg2 frame valid i/o cmos none high-z mpstr mpeg2 frame start i/o cmos none high-z mpdata mpeg2 data pin (serial mode) i/o cmos none high-z ir infrared input for usb2.0 mode i/o cmos none high-z tunsda,tunscl 2-wire bus for tuner i/o open drain pull-up high-z ifagc,rfagc agc control for rf and if i/o open drain pull-up high-z vbus vbus pin for usb 2.0 i/o cmos pull-up high-z clko clock out for second ts i/o cmos none clock www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 15 table 3: analog i/o pin detailed description. pin name pin description type dp/dm dp/dm pins for usb2.0 analog i/o xtali_usb/ xtalo_usb crystal pins for usb2.0. analog i/o xin, xout crystal pins for chip clock. analog i/o rrefx reference bias pin. please connect 20k resistor to ground. analog i/o vrefp, vrefn, vcm reference voltages for adc. analog i/o vip/vin differential analog input. analog i/o table 4: power/ground pin detailed description. pin name pin description nominal voltage vdd digital core power 1.8v vss digital core ground 0v vddio digital i/o power 3.3v vssio digital i/o ground 0v avddh_usb power for usb2.0 3.3v vdda33 power for analog 3.3v 3.3v vdda18 power for analog 1.8v 1.8v vdda18_pll power for clocking 1.8v gnda/agnd_usb analog ground 0v . table 5: strapping pins sampled at the rising edge of the reset signal. pin name strapping usage normal usage s addr0/gpio0, s addr0/gpio0/lock4 determine the 2-wire bus address. see table 7 of section 4.6.1 gpio strapclk/gpio1, strapclk/gpio1/lock3 main crystal frequency information. gpio pwrdw/lock2 main crystal frequency information. power down control or gpio (register programmed) strap/lock1 test mode select. pull- down for normal mode. pull-up for test mode. gpio www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 16 4 functional description 4.1 operation modes af9013/13s/15 operates in several modes, including the mpeg2 ts m ode for af9013/13s , and the standard usb2.0 and mpeg2/usb concurrent modes for af9015. the operation mode of af9015 is chosen by appropriately setting the 2-wire bus addr ess using the strapping pin saddr0 according to table 6. details of the 2-wire bus interface are g iven in section 4.6. table 6: af9015 operation mode selection. strapping logic level of saddr0 af9015 operation mode low standard usb 2.0 high concurrent 4.1.1 mpeg ts mode ( af9013/13s only) in the mpeg ts mode, af9013/13s outputs mpeg2 transport stream through either the parallel or serial mpeg2 transport stream interface. a backend mpeg2 decoder is used to interface with af9013/13s using the 2-wire bus and the mpeg2 ts interface si gnals. more detailed signal and timing descriptions of the 2-wire bus and mpeg2 transport stream interface can be found in sections 4.6 and 4.7, respectively. 4.1.2 standard usb2.0 mode ( af9015 only) in the standard usb 2.0 mode, af9015 communicates with a pc through the embedded usb 2. 0 interface. the mpeg-2 transport stream decoded by af9015 and control/status signals are all encapsulated in the usb frames. in the standard us b 2.0 mode af9015 also accepts a secondary mpeg2 transport stream input from the mpeg-2 serial interface and delivers it to the pc through the embedded usb 2.0 interface. this secondary transpo rt stream can, for example, come from an af9013/13s , thus enabling the pc to simultaneously receive an d display two transport streams transmitted on different rf frequencies. more deta iled description of the af9015 mpeg2 transport stream interface and usb 2.0 interface can be found in sections 4.7 and 4.8, respectively. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 17 4.1.3 concurrent mode ( af9015 only) in the mpeg/usb concurrent mode, af9015 chip outputs mpeg2 transport stream through the se rial mpeg2 interface. a backend mpeg2 decoder is used t o interface with af9015 using the 2-wire bus and mpeg2 ts serial interface. concurrently, af9015 outputs the same mpeg transport stream to a pc through the usb port. more detailed signal and tim ing descriptions of the 2-wire bus and mpeg2 transport stream interface can be found in sections 4.6 and 4.7, respectively. more detailed descript ion of the af9015 usb 2.0 interface can be found in section 4.8. 4.2 analog interface 4.2.1 crystal oscillator af9013/13s/15 has an on-chip crystal amplifier for clock generat ion. this amplifiers normal operation current is less than 0.5ma when generating a 28mhz clock. no extra resistor is necessary between xin and xout since it is already embedded. af9015 also needs an additional 12mhz xtali/xtalo p air for 12mhz clock generation for the embedded usb 2.0 interface. the af9013/13s/15 clocking circuit requires a stable reference clock . it can be provided by either of the following two methods: 1. connect a crystal across the oscillator pins (xi n and xout), or 2. connect an external clock source to pin xin, and leave xout open. the selection of the crystal clock frequency for ad c depends on the if frequency, dvb-t channel bandwidth, and adc sampling frequency. an example for the 8mhz bandwidth is to use a 20.48mhz crystal for 36.17 or 4.57mhz if frequencies. af9015 also provides a buffered clock output which, for e xample, can be used to drive a second af9013/13s/15 . 4.2.2 analog-to-digital converter (adc) a 10-bit analog-to-digital converter is used in the front-end of af9013/13s/15 . the adc supports direct sampling of 36.17 mhz or 43.75mhz and near-zero 4.5 7 mhz if signals, as well as 6, 7, 8 mhz ofdm channel bandwidth. its maximum differential input i s 2 volt peak-to-peak. the adc clock input is directly from crystal output or from internal pll. 4.2.3 automatic gain control (agc) the af9013/13s/15 agc monitors the adc output samples and generates t wo pulse-density-modulated (pdm) control signals for the rf and if voltage gai n amplifiers (vgas) as shown in figure 6. a single -bit interface is used to reduce the number of connectio n pins. the amplifier gain is increased or decrease d to maintain the adc output at a target level. the dua l agc mechanism combined with the take-over-point (top) operation permit optimal control of both gain amplifiers to minimize noise. figure 7 shows an example of the top operation. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 18 the af9013/13s/15 agc is fully programmable to meet the needs of dif ferent tuners or applications. specifically, the target adc output level is progra mmable. the vga control voltage range can be digitally controlled to avoid nonlinear regions of the gain amplifiers. the loop bandwidth of both rf and if agcs can be independently adjusted. also, vgas w ith inverted or non-inverted voltage-gain curve can be supported. the rf agc control can be disabled for tuners with built-in rf agc control. disabling the rf agc control is done by register programming. figure 6: dual agc control. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 19 rf agc if agc signal strength vga control voltage if top rf top rf agc if agc signal strength vga control voltage if top rf top figure 7: top operations for inverted (left) and no n-inverted (right) voltage-gain curves. 4.3 cofdm digital signal processing 4.3.1 initialization several important system parameters need to be prog rammed correctly in order to insure proper operations of af9013/13s/15 . these include the adc sampling frequency, tuner if frequency, whether the tuner introduces spectral inversion, and the dv b-t channel bandwidth, which can be 6, 7, or 8 mhz. 4.3.2 time-domain signal processing before the received signals are converted to the fr equency domain via fast fourier transform (fft), several complicated digital signal processing algor ithms are implemented to handle different impairmen ts encountered in the transmission environment. an automatic gain control (agc) module measures the received signal strength to determine the correct tuner gain-control signal values. based on differe nt characteristics of different tuners used, the ag c module can be programmed to accommodate any specifi c tuner gain-control curve and also the best take- over-point (top). impulse noise is also actively searched and elimina ted. co-channel interference (cci) due to pal, nicam, or any other source is adaptively detected and notched out if necessary. no prior knowledge of th e cci location is needed, and the activation of the cci cancellation filter is automatic. the if signal sampled by af9013/13s/15 adc is digitally converted to a complex signal in the baseband at the elementary period, which is 7/64us for 8mhz channels, 1/8us for 7mhz channels, and 7/48us for 6mhz channels. adjacent channel interference (aci) is removed by a very sharp digital filter whose bandwidth is independent of the dvb-t channel bandwidth. theref ore, a signal 8mhz saw filter is sufficient for 6, 7 or 8 mhz channels. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 20 4.3.3 frequency-domain signal processing in the frequency domain, a transmission parameter s ignaling (tps) decoder is implemented to extract system parameters, including the constellation, hie rarchy information, code rate, fft mode, and guard interval. the channel estimator estimates and the amplitude a nd phase distortion caused by the transmission channel and radio frequency (rf) front-end. the co mmon phase error introduced by the rf front-end is also estimated. these distortions are then compens ated by the frequency domain equalizer (feq). the equalized output of feq is then used to generat e the input to forward-error-correction (fec) for further processing. 4.3.4 synchronization loop an all-digital synchronization loop is implemented in af9013/13s/15 to determine and track the correct fft window position, track and compensate for the c arrier frequency offset caused by the front-end tun er, and track and compensate for the clock jitter intro duced by the local crystal. since the synchronizat ion loop is entirely digital, no analog vcxo is necessa ry. the af9013/13s/15 synchronization loop is capable of correcting carrier frequency offsets of up to 500 khz and clock offsets of up to 100ppm. 4.4 forward error correction the symbol and bit de-interleavers compliant with e tsi en 300 744 are implemented in the af9013/13s/15 forward error correction (fec). a viterbi decoder with de-puncturing is used to decode the punctured convolutional code. a shortened (204 , 188) read-solomon decoder that corrects up to eight byte-errors in a 204 byte frame follows the v iterbi decoder to extract the mpeg2 transport strea m packets. a fail signal is alerted when the number of error bytes exceeds eight, and the same input is bypassed to the output in this case. finally, de-s crambler reverses the scrambling process, and the 0 x47 to 0xb8 sync byte inversion is removed after the de -scrambler. 4.5 performance monitoring af9013/13s/15 provides a complete set of registers for monitorin g the performance and status of the demodulator. the parameters that can be monitored and derived include the sampling clock and carrier frequency offsets, tps and mpeg-2 lock signals, tps parameters, bit error rates and packet error rates , signal quality, and signal strength. details on pe rformance monitoring can be found in af9013/13s/15 design manual . 4.6 2-wire interface af9013/13s/15 provides two independent 2-wire interfaces for com municating with the external host and tuner. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 21 4.6.1 host interface the af9013/13s/15 host 2-wire interface uses, respectively, pins sda for the serial data and scl for the serial clock. the bus address of the af9013/13s/15 2-wire host interface is determined by the strappin g pin saddr0. when af9013/13s/15 is first powered up, the reset pin should be held low. as the reset pin transitions from low to high, the logic l evel of the strapping pin saddr0 is latched to determine the 2-wire bus address, as shown in table 7. for af9015 , the logic level of the strapping pin saddr0 also determines its operation mode, as descr ibed in section 4.1. table 7: af9013/13s/15 2-wire bus address mapping table. saddr0 at strapping 2-wire bus address remarks low 0x38 af9015 works in the standard usb2.0 mode high 0x3a af9015 works in the concurrent usb2.0 mode the af9013/13s/15 host 2-wire interface supports both read and write operations. the circuit works as a slave transmitter in the read operation mode and slave receiver in the write operation mode. details on using the 2-wire host interface can be f ound in af9013/13s/15 design manual. 4.6.2 tuner interface af9013/13s/15 also provides a secondary 2-wire interface for com municating with the external tuner. it uses pins tunsda for serial data and tunscl for ser ial clock. the circuit works as a master transmitter in the write operation mode and master receiver in the read operation mode. details on us ing the 2- wire tuner interface can be found in af9013/13s/15 design manual. 4.7 mpeg-2 transport stream interface the af9013/13s/15 mpeg-2 transport stream interface pins and their me anings are listed in table 8. the mpeg-2 transport stream interface of af9013/13s/15 offers both parallel and serial outputs, as well as serial input in the af9015 standard usb2.0 mode. for af9013/13s operating in the mpeg-2 ts mode, the mpeg-2 transport stream interface can ope rate in the parallel output mode, serial output mod e, or be disabled. an example timing diagram of the p arallel output mode is shown in figure 8. for the serial output mode the mpeg-2 ts data can be config ured to be output on pins mpdata7 or mpdata0. on the other hand, for af9015 operating in the standard usb2.0 mode, the mpeg-2 transport stream interface is an input interface that accepts mpeg-2 transport streams in a serial fashion. the mpeg-2 ts data pin is mpdata. finally, for af9015 operating in the concurrent mode, the mpeg-2 trans port stream interface is a serial output interface. a t able of af9013/13s/15 mpeg-2 ts interface modes is given in table 9. the af9013/13s/15 mpeg-2 transport stream interface is fully configu rable. the list of configurable parameters is shown in table 10. details on config uring the af9013/13s/15 mpeg-2 ts interface are available in af9013/13s/15 design manual. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 22 mpclk mpdata[7:0] mpfrm mpstr mpfail sync byte 1 byte 2 byte 3 byte 4 figure 8: an example of mpeg2 parallel interface ti ming diagram. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 23 table 8: af9013/13s/15 mpeg-2 ts interface pins. pin name i/o description mpclk in/out mpeg clock mpdata7, mpdata6, mpdata5, mpdata4, mpdata3, mpdtat2, mpdata1, mpdata0 out mpeg transport stream data for af9013/13s . 8-bit in the parallel mode and 1-bit in the serial mode. mpdata0 or mpdata7 can be the output pin in the serial mode. mpdata in/out mpeg transport stream data (serial in put or output) for af9015 . mpfrm in/out mpeg data valid mpstr in/out mpeg packet sync pulse mpfail in/out mpeg uncorrectable packet table 9: the af9013/13s/15 mpeg-2 ts interface mode selection. part number operation mode mpeg-2 transport stream interface operation modes serial output. data is on pins mpdata7 or mpdata0. parallel output af9013/13s mpeg-2 ts mode disabled standard usb2.0 mode serial input. data is on pin mpdata. af9015 concurrent mode serial output data is on pin mpdata table 10: configurable parameters of the af9013/13s/15 mpeg-2 ts interface. parameter selections www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 24 input/output mode parallel output serial output serial input ( af9015 only) output data pin of serial mode. mpdata7 or mpdata0 ( af9013/13s only) bit-order for parallel mode: mpdata7 can be msb or lsb for serial input and output modes: can be msb first or lsb first. style of the mpeg-2 sync byte mpeg-2 style or dvb-t style. signal polarity mpclk, mpfrm, mpstr, and mpfail can be independently configured to be active high or low. the style of mpfrm continuous or gapped. the gap between consecutive 188-byte payloads in units of byte times. 0 ~ 31 mpstr assertion for the serial output mode, select whether mpstr is asserted only for the first bit or for all bits of the first byte. asserted for all bits of the first byte or for the first bi t only. mpclk frequency configurable mpstr pin for the serial input mode for the serial input mode can be used or wired to ground. output driving capability configurable with optional slew-rate control www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 25 4.7.1 parallel output interface for af9013/13s , when the mpeg-2 ts interface is programmed to be the parallel output mode, each byte of the payload of the mpeg-2 transport stream will be output to mpdata7~mpdata0 in parallel. mpfrm is asserted when a payload byte is being outp ut on mpdata7~mpdata0. mpstr is asserted at the first payload byte of each transport stream packet. mpfail is asserted throughout the entire duration of any erroneous transport stream packet. note that there can be gaps between bytes in mpfrm. example timing diagrams with continuous and gapped mpfrm are shown in figure 9 and figure 10, r espectively. mpclk cccccccccccc:::cccccccccccccccc mpdata[7:0] zmssssssssss:::ssssizzzmsssssss mpfrm lkhhhhhhhhhh:::hhhhtlllkhhhhhhh mpstr lktlllllllll:::llllllllktllllll mpfail lkhhhhhhhhhh:::hhhhtlllllllllll figure 9: timing diagram with continuous mpfrm in p arallel mode. mpclk ccccccccccccccccccccc:::ccccccccc mpdata[7:0] zmsssdsdsdsssdsdsdsss:::dizzzmsss mpfrm lkhhtktktkhhtktktkhht:::ktlllkhht mpstr lktllllllllllllllllll:::lllllktll mpfail lkhhh hhhhhhhhhhhhhhhh:::htlllllll figure 10: timing diagram with gapped mpfrm in para llel mode. 4.7.2 serial output interface in the serial output mode, the payloads of mpeg-2 t ransport stream will be serially output on mpdata7 or mpdata0 for af9013/13s or on mpdata for af9015 . in this mode, mpstr can be asserted at the first bit or first 8 bits of the payload of the tra nsport stream. furthermore, there can be gaps in m pfrm, but there can be no gaps within the 8 bits of a byt e. example timing diagrams of mpfrm without and with gaps are shown in figure 11 and figure 12, res pectively. finally, same as in the parallel mode, for any error packet, mpfail is asserted throughout the entire duration of any erroneous transport stream packet. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 26 mpclk cccccccccccc:::cccccccccccccccc mpdata[0]or[7] zmssssssssss:::ssssizzzmsssssss mpfrm lkhhhhhhhhhh:::hhhhtlllkhhhhhhh mpstr(bit length) lktlllllllll:::llllllllktllllll mpfail lkhhhhhhhhhh:::hhhh tlllllllllll figure 11: timing diagram of continuous mpfrm signa l in serial mode. mpclk ccccccccccccccccccccccccccccc mpdata[0]or[7] mssssssssddddddddssssssssdddd mpfrm khhhhhhhtlllllllkhhhhhhhtllll mpstr(byte length) khhhhh hhtllllllllllllllllllll mpfail khhhhhhhhhhhhhhhhhhhhhhhhhhhh figure 12: timing diagram of gapped mpfrm signal in serial mode. 4.7.3 serial input interface (af9015 only) the mpeg2 ts interface of af9015 can also become an input interface for accepting a secondary mpeg2 ts stream and forwarding to the pc through th e usb2.0 interface. only serial data is supported for receiving the secondary mpeg2 ts stream. an ex ample timing diagram for the af9015 mpeg2 ts input interface is shown in figure 13. mpclk cccccccccccc:::cccccccccccccccc mpdata[0] zmssssssssss:::ssssizzzmsssssss mpfrm lkhhhhhhhhhh:::hhhhtlllkhhhhhhh mpstr(bit length) lktlllllllll:::llllllllktllllll figure 13: timing diagram of the af9015 mpeg-2 ts serial input interface. mpstr of af9015 can be wired to the ground if mpstr is not availab le from the mpeg ts stream provider. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 27 4.8 usb interface ( af9015 only) af9015 supports usb 2.0 standard with many configurable pa rameters in the endpoint 0 descriptors. 4.8.1 usb descriptors most strings and parameters in the descriptors are configurable in the external eeprom, including: device descriptors: vender id, product id, device release number, manufacturer string index, product string index, serial number string index, c onfiguration characteristics (self-powered, remote wake-up, etc.), max power consumption, and interru pt endpoint (endpoint 3) polling interval; and strings: the string description of the manufacturer and the product and the serial number. these strings are defined in usb 2.0 standard. see af9013/13s/15 design manual for details on the external eeprom. 4.8.2 usb control protocol 4.8.2.1 default endpoint (endpoint 0) endpoint 0 is the same as defined in usb 2.0 standa rd. 4.8.2.2 control messages control messages are sent through a request-and-rep ly model. any request packet corresponds to a reply packet, unless the communication is malfuncti oning. a sequence number field is employed in each control packet to resolve the late reply and duplic ate request/reply problems. the available control messages include those for ge tting the current configuration, downloading the firmware, computing firmware checksum, booting af9015 , copying the firmware to a slave device, reading and writing the af9015 memory, as well as 2-wire bus control messages, sof tware reset control messages, and control unit command control messages . 4.8.2.3 data messages data messages convey the mpeg2 transport streams re ceived by af9015 . www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 28 4.9 infrared (ir) interface ( af9015 only) af9015 supports two ir protocols: nec and rc6. the ir fun ction can be enabled or disabled and the ir protocol can be selected by appropriately setting t he corresponding fields in the external eeprom. if the ir function is enabled, af9015 is considered as a usb composite device with hid. otherwise af9015 is a usb single device. more details on eeprom setting s are available in af9013/13s/15 design manual . the af9015 ir decoder decodes raw signals received from the i r photo-receiver. then the demodulated signals are converted to hid (human interface devic es) format according to a translation table that is downloaded from the driver via the memory write pro tocol (see section 4.8.2.2 for more details on usb control protocols). at last the usb host receives i r messages via usb endpoint 3. more details of the af9015 ir interface are available in af9013/13s/15 design manual. 4.9.1 the function key and alternative keys the function key (fn) is used to create alternative key sequences for a remote control. when fn of a remote control is pressed, an alternative key seque nce is initiated, and any keys pressed are consider ed alternative if they are pressed within a predefin ed expiration time after the previous key press. th is design enables a remote control with fewer keys (bu ttons) to almost double its effective number of k eys. af9015 will not send any key when only the function key is pressed alternative keys are supported in af9015 as mentioned in af9013/13s/15 design manual. 4.10 the external eeprom an external eeprom can be used for storing usb rela ted information, firmware, and possibly other hardware related information in systems using af9015 . the content and format of the external eeprom is given in great detail in af9013/13s/15 design manual. 4.11 boot scheme af9013/13s/15 operates in the mpeg2 ts, standard usb2.0, or mpeg /usb concurrent modes, each with its own booting scheme. details of the operat ion modes are available in section 4.1. in the mpe g- 2 ts mode for af9013/13s and concurrent mode of af9015 , the booting process is a simplex process, in the sense that information only flows from the host to af9013/13s . af9013/13s/15 does not send any information to the host. however, af9013/13s/15 does make the download status available to the hos t by writing the status to an internal register for t he host to poll. on the other hand, the booting sc heme of the standard usb2.0 download mode is a duplex proce ss in which requests from the host is responded by replies from af9015 . furthermore, the af9015 usb firmware is also involved in this scheme to in form the host that the usb firmware is running. details of the boot schemes are available in af9013/13s/15 design manual . www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 29 5 electrical characteristics 5.1 absolute maximum ratings table 11: af9013/13s/15 absolute maximum ratings. parameter symbol min max unit i/o power voltage vddio -0.3 3.6 v digital core power voltage vdd -0.3 2.0 v analog 3.3v power voltage vdda33 -0.3 3.6 v analog 1.8v power voltage vdda18 -0.3 2.0 v voltage on input pins vi -0.3 vddio+0.3 v voltage on output pins vo -0.3 vddio+0.3 v storage temperature tstg -40 150 oc junction temperature tj 125 oc ambient operating temperature (commercial) ta 0 70 oc 0(m/s) 1(m/s) 2(m/s) junction-ambient thermal resistance for 64-pin chip and 4-layers pcb rth(j-a) 37 35 32.6 oc/w 0(m/s) 1(m/s) 2(m/s) junction-ambient thermal resistance for 56-pin chip and 4-layers pcb rth(j-a) 21.5 18.9 17.1 oc/w www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 30 5.2 dc electrical characteristics table 12: af9013/13s/15 dc electrical characteristics (not applicable for 9013a/13as/15a ). note: vdd=1.8v, vddio=3.3v and ta=25c unless otherw ise specified. parameter symbol test condition min typ max unit digital core power voltage vdd 1.6 1.8 2.0 v i/o power voltage vddio 3.0 3.3 3.6 v analog 1.8v power voltage vdda18 1.6 1.8 2.0 v analog 3.3v power voltage vdda33 3.0 3.3 3.6 v digital core power supply current i vdd af9013/13s typical air reception * 103 ma i/o power supply current i vddio af9013/13s typical air reception * 3 ma analog 1.8v power supply current i vdda18 af9013/13s typical air reception * 5 ma analog 3.3v power supply current i vdda33 af9013/13s typical air reception * 27 ma power consumption (operating) p op af9013/13s typical air reception * 293 mw digital core power supply current i vdd af9015 typical air reception * 107 ma i/o power supply current i vddio af9015 typical air reception * 27 ma analog 1.8v power supply current i vdda18 af9015 typical air reception * 5 ma analog 3.3v power supply current i vdda33 af9015 typical air reception * 27 ma power consumption (operating) p op af9015 typical air reception * 380 mw current consumption (suspend mode) i sus 290 ua high level input voltage vih 2.0 v low level input voltage vil 0.8 v www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 31 input capacitance cin 3 pf high level output voltage voh 3.0 v low level output voltage vol 0.4 v high/low level output current ioh/iol digital outpu t pins 0 4 ma high/low level output current ioh/iol 5v tolerant o pen-drain 0 2 ma * the air signal being received uses 8k, 16qam, cr=2 /3, gi=1/4, and 6mhz. the adc sampling clock is 20.48mhz. table 13: af9013a/13as/15a dc electrical characteristics (not applicable for 9013/13s/15 ). note: vdd=1.8v, vddio=3.3v and ta=25c unless otherw ise specified. parameter symbol test condition min typ max unit digital core power voltage vdd 1.6 1.8 2.0 v i/o power voltage vddio 3.0 3.3 3.6 v analog 1.8v power voltage vdda18 1.6 1.8 2.0 v analog 3.3v power voltage vdda33 3.0 3.3 3.6 v digital core power supply current i vdd af9013a/13as typical air reception * 83 ma i/o power supply current i vddio af9013a/13as typical air reception * 2 ma analog 1.8v power supply current i vdda18 af9013a/13as typical air reception * 4 ma analog 3.3v power supply current i vdda33 af9013a/13as typical air reception * 27 ma power consumption (operating) p op af9013a/13as typical air reception * 253 mw digital core power supply current i vdd af9015a typical air reception * 90 ma i/o power supply current i vddio af9015a typical air reception * 27 ma analog 1.8v power suppl y current i vdda18 af9015a typical air reception * 5 ma www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 32 analog 3.3v power supply current i vdda33 af9015a typical air reception * 27 ma power consumption (operating) p op af9015a typical air reception * 349 mw current consumption (suspend mode) i sus 7 ua high level input voltage vih 2.0 v low level input voltage vil 0.8 v input capacitance cin 3 pf high level output voltage voh 3.0 v low level output voltage vol 0.4 v high/low level output current ioh/iol digital outpu t pins 0 4 ma high/low level output current ioh/iol 5v tolerant o pen-drain 0 2 ma www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 33 5.3 analog characteristics table 14: af9013/13s/15 analog electrical characteristics. parameter symbol test condition min typ max unit adc resolution 10 bit adc input range, register programmable vinpp 1 2 v adc vrefp voltage vrefp 1.6 2.2 v adc vrefn voltage vrefp 0.9 1 1.4 v adc vcm voltage vcm 1.35 1.5 1.65 v differential input bandwidth fin 50 mhz crystal input capacitance ccry 2 pf 5.4 ac electrical characteristics 5.4.1 mpeg-2 ts output figure 14: af9013/13s/15 mpeg-2 ts output timing diagram. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 34 table 15: af9013/13s/15 mpeg-2 ts output timing. parameter description min. max. unit t/2 a half mpclk (40mhz) clock cycle ns t dmin minimum valid delay t/2 - 3 ns t dmax maximum valid delay t/2 + 3 ns 5.4.2 mpeg-2 ts input ( af9015 only) figure 15: af9015 mpeg-2 ts input timing diagram. table 16: af9015 mpeg-2 ts input timing parameter requirement unit input set-up time 0 ns input hold time 6.26 ns www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 35 5.4.3 2-wire bus output figure 16: af9013/13s/15 2-wire bus output timing diagram. table 17: af9013/13s/15 2-wire bus output timing. parameter description min. max. unit t dmin minimum valid delay of 2-wire bus output 317 ns t dmax maximum valid delay of 2-wire bus output 334 ns www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 36 5.4.4 2-wire bus input t dsetup t dhold scl sda t/2 figure 17: af9013/13s/15 2-wire bus input timing diagram. table 18: af9013/13s/15 2-wire bus input timing. parameter description min. max. unit t dsetup 2-wire bus input setup time 2 t/2 -2 ns t dhold 2-wire bus input hold time 2 t/2 -2 ns www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 37 6 mechanical specification 6.1 lqfp-64 outline dimensions figure 18: lqfp-64 outline dimensions. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 38 6.2 qfn-56 outline dimensions figure 19: qfn-56 outline dimensions. www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 39 7 register list table 19: af9013/13s/15 register list. register name register name register name register name address address address address bits bits bits bits access access access access register description register description register description register description default default default default 0xd07c reg_aagc_rf_gain[7:0] 7:0 rs return agc rf gain value 8'h0 0xd07d reg_aagc_if_gain[7:0] 7:0 rs return agc if gain value 8'h0 0xd140 reg_bfs_fcw[7:0] 7:0 rw bfs frequency control word 8'h0 0xd141 reg_bfs_fcw[15:8] 7:0 rw bfs frequency control word 8'h0 0xd142 reg_bfs_fcw[22:16] 6:0 rw bfs frequency control word 7'h0 0xd150 fcw_q[7:0] 7:0 rs carrier frequency offset value 8'h0 0xd151 fcw_q[15:8] 7:0 rs carrier frequency offset value 8'h0 0xd152 fcw_q[22:16] 6:0 rs carrier frequency offset value 7'h0 0xd180 reg_f_adc[7:0] 7:0 rw adc frequency 8'h0 0xd181 reg_f_adc[15:8] 7:0 rw adc frequency 8'h0 0xd182 reg_f_adc[23:16] 7:0 rw adc frequency 8'h0 0xd190 intp_mu[7:0] 7:0 rs sampling frequency offset. 8'h0 0xd191 intp_mu[15:8] 7:0 rs sampling frequency offset. 8'h0 0xd192 intp_mu[23:16] 7:0 rs sampling frequency offset. 8'h0 0xd1a0 reg_agc_rst 0 rws reset rf agc 1'h0 rf_agc_en 1 rw enable rf agc 1'h0 agc_lock 6 rws indicate agc lock 1'h0 0xd2c0 www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 40 fpcc_cp_corr_signn[7:0] 7:0 rs pilot error count 8'h0 0xd2e1 reg_qnt_vbc_rdy 3 rws vbc ready indicator 1'h0 0xd2e2 reg_qnt_vbc_sframe_num[7:0] 7:0 rw vbc count (unit: super-frames) 8'h1 0xd2e3 reg_qnt_vbc_err[7:0] 7:0 rs vbc error count 8'h0 0xd2e4 reg_qnt_vbc_err[15:8] 7:0 rs vbc error count 8'h0 0xd2e5 reg_qnt_vbc_err[23:16] 7:0 rs vbc error count 8'h0 0xd2e6 reg_qnt_vbc_ccid_mode 0 rw busy status of 0xd2e3, 0xd2e4, 0xd2e5. 0: available (not busy) 1: unavailable (busy) 1'h0 0xd330 tpsd_lock 3 rws to declare whether tps is lock or not. note: ofsm should "read clear" this register. 1'h0 tpsd_s19 4 rs s19 of length indicator. 0: cell_id is not supported 1: cell_id is supported. 1'h0 tpsd_s17 5 rs s17 of length indicator. 0: reserved bits are not used 1: reserved bits are used 1'h0 0xd385 rsd_packet_unit[7:0] 7:0 rw rbc packet number per unit for error count 8 'h0 0xd386 rsd_packet_unit[15:8] 7:0 rw rbc packet number per unit for error count 8 'h1 0xd387 reg_rsd_bit_err_cnt[7:0] 7:0 rs rbc error bit counter 8'h0 . 0xd388 reg_rsd_bit_err_cnt[15:8] 7:0 rs rbc error bit counter 8'h0 . 0xd389 reg_rsd_bit_err_cnt[23:16] 7:0 rs rbc error bit counter 8'h0 0xd38a reg_rsd_abort_packet_cnt[7:0] 7:0 rs rbc abort packet counter 8'h0 . 0xd38b reg_rsd_abort_packet_cnt[15:8] 7:0 rs rbc abort packet counter 8'h0 0xd3c0 www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 41 reg_tpsd_txmod[1:0] 1:0 rw s38~s39 transmission mode 2'h0 reg_tpsd_gi[1:0] 3:2 rw s36~s37 guard interval 2'h0 reg_tpsd_hier[2:0] 6:4 rw s27~s29 hierarchy information 3'h0 0xd3c1 reg_bw[1:0] 3:2 rw channel bandwidth 2'h0 reg_dec_pri 4 rw decode priority 1'h0 reg_tpsd_const[1:0] 7:6 rw s25~s26 constellation 2'h0 0xd3c2 reg_tpsd_hpcr[2:0] 2:0 rw code rate, hp stream s30~s32 3'h0 reg_tpsd_lpcr[2:0] 5:3 rw code rate, lp stream s33~s35 3'h0 0xd400 i2c_m_slave_addr[7:0] 7:0 rw 2-wire bus master slave address 8'h0 0xd401 i2c_m_data1[7:0] 7:0 rw 2-wire bus master mail box data1 8'h0 0xd402 i2c_m_data2[7:0] 7:0 rw 2-wire bus master mail box data2 8'h0 0xd403 i2c_m_data3[7:0] 7:0 rw 2-wire bus master mail box data3 8'h0 0xd404 i2c_m_data4[7:0] 7:0 rw 2-wire bus master mail box data4 8'h0 0xd405 i2c_m_data5[7:0] 7:0 rw 2-wire bus master mail box data5 8'h0 0xd406 i2c_m_data6[7:0] 7:0 rw 2-wire bus master mail box data6 8'h0 0xd407 i2c_m_data7[7:0] 7:0 rw 2-wire bus master mail box data7 8'h0 0xd408 i2c_m_data8[7:0] 7:0 rw 2-wire bus master mail box data8 8'h0 0xd409 i2c_m_data9[7:0] 7:0 rw 2-wire bus master mail box data9 8'h0 0xd40a i2c_m_data10[7:0] 7:0 rw 2-wire bus master mail box data10 8'h0 0xd40b i2c_m_data11[7:0] 7:0 rw 2-wire bus master mail box data11 8'h0 0xd40c i2c_m_data12[7:0] 7:0 rw 2-wire bus master mail box data12 8'h0 0xd40d i2c_m_data13[7:0] 7:0 rw 2-wire bus master mail box data13 8'h0 www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 42 0xd40e i2c_m_data14[7:0] 7:0 rw 2-wire bus master mail box data14 8'h0 0xd40f i2c_m_data15[7:0] 7:0 rw 2-wire bus master mail box data15 8'h0 0xd410 i2c_m_data16[7:0] 7:0 rw 2-wire bus master mail box data16 8'h0 0xd411 i2c_m_data17[7:0] 7:0 rw 2-wire bus master mail box data17 8'h0 0xd412 i2c_m_data18[7:0] 7:0 rw 2-wire bus master mail box data18 8'h0 0xd413 i2c_m_data19[7:0] 7:0 rw 2-wire bus master mail box data19 8'h0 0xd414 i2c_m_cmd_rw 0 rw 2-wire bus master command byte read/write specification 1'h0 i2c_m_cmd_rwlen[3:0] 6:3 rw 2-wire bus master command byte read/write length specification 4'h0 0xd415 i2c_m_status_cmd_exe 0 rw 2-wire bus master status execution indicator 1 'h0 i2c_m_status_wdat_done 1 rws 2-wire bus master write done indicator 1'h0 i2c_m_status_wdat_fail 2 rws 2-wire bus master write fail indicator 1'h0 i2c_m_status_rdat_rdy 3 rws 2-wire bus master read data ready 1'h0 0xd416 i2c_m_period[7:0] 7:0 rw 2-wire bus master period setting. 8'h0 0xd417 i2c_m_reg_msb_lsb 0 rw 2-wire bus master register: msb/lsb selector 1 'h1 reg_sample_period_on_tuner 2 rw sample period on tuner 1'h0 reg_sel_tuner 3 rw 2-wire bus master register: 2-wire bus traffic selector for tuner 1'h0 0xd500 mpeg_par_mode 1 rw mpeg-2 output is parallel 1'h0 mpeg_ser_mode 2 rw mpeg-2 output is serial 1'h0 mpeg_ser_do7 3 rw mpeg-2 serial output pin number. 0: output from data0, 1: output from data1 1'h0 data_access_disable 4 rw disable mpeg-2 data access 1'h0 keep_sf_sync_byte 5 rw keep super frame sync byte 1'h0 no_modify_tei_bit 6 rw disable modification of tei 1'h0 0xd501 mpeg_clk_pol 0 rw the polarity of mpclk signal 1'h0 www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 43 0: data changed after positive edge of mpclk 1: data changed after negative edge of mpclk mpeg_vld_pol 1 rw the polarity of mpfrm signal 0: active high (set to 1 to indicate valid data) 1: active low 1'h0 mpeg_sync_pol 2 rw the polarity of mpstr signal 0: active high (set to 1 to indicate frame sync) 1: active low 1'h0 mpeg_err_pol 3 rw the polarity of mpfail signal 0: active high (set to 1 to indicate error) 1: active low 1'h0 mpeg_clk_gated 4 rw the style of mpclk signal 0: free running mpclk 1: gated mpclk when gated clock is selected, there is no clock running when no valid data is available. 1'h0 msdo_msb 5 rw msb or lsb first on the mpeg data output 0: lsb first 1: msb first 1'h1 mssync_len 6 rw mpstr is asserted for the first bit or byte 0: asserted for whole bits of first byte 1: asserted for first bit only 1'h0 0xd502 reg_mpeg_full_speed 4 rw full speed in mpeg interface 1'h0 0xd503 pid_en 0 rw pid_en 1'h0 pid_rst 1 rws reset pid table 1'h0 pid_complement 2 rw pid table complement; 0: pid out if table hit, 1: p id out if table not hit. 1'h0 0xd504 pid_index[4:0] 4:0 rws pid index 5'h0 pid_index_en 5 rws enable current pid index 1'h0 0xd505 pid_dat_l[7:0] 7:0 rw pid data register (bit 7-0) 8'h0 0xd506 pid_dat_h[4:0] 4:0 rw pid data register (bit 12-8) 5'h0 0xd507 reg_mp2_sw_rst 2 rw software reset 1'h1 reg_mpeg_vld_tgl 3 rw mpfrm toggle select 1'h0 sync_byte_locked 6 rs indicate sync_byte_locked 1'h0 reg_mp2_sw_rst2 3 rw software reset 1'h1 www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 44 0xd50c reg_tpsd_bw_mp2if[1:0] 1:0 rw programmed bw 2'h0 reg_tpsd_gi_mp2if[1:0] 3:2 rw programmed gi 2'h0 reg_tpsd_cr_mp2if[2:0] 6:4 rw programmed cr 3'h0 0xd50d reg_tpsd_cons_mp2if[1:0] 1:0 rw programmed constellation 2'h0 reg_fw_table_en 2 rw programmed tpsd enable 1'h0 0xd510 reg_packet_gap[4:0] 4:0 rw size of the gap between 188 packets 5'h10 0xd520 reg_ts_clk_inv 0 rw invert the input clock of 2nd ts. 1'h0 reg_ts_dat_inv 1 rw invert the input data of 2nd ts. 1'h0 reg_ts_lsb_1st 2 rw 0: the input serial data of 2nd ts is msb first; 1: the input serial data of 2nd ts is lsb first. 1'h0 reg_ts_capt_bg_sel 3 rw 0: the 2nd ts input sync signal is not used to sync data; 1: the 2nd ts input sync signal is used to sync data 1'h1 reg_mp2if_stop_en 4 rw 0: back pressure scheme is not applied; 1: enable back pressure to do flow control of the 2nd ts. 1'h0 reg_mp2if2_pes_base 5 rw 0: the 2nd ts data can be dropped anytime when the buffer is full; 1: the 2nd ts data will be dropped by the unit of 188 bytes. 1'h0 reg_ts_sync_inv 6 rw invert the input signal "sync" of 2nd ts. 1'h0 reg_ts_vld_inv 7 rw invert the input signal "valid" of 2nd ts. 1'h 0 0xd607 reg_bypass_host2tuner 2 rw 0:disable 1:enable, create bypass path from host to tuner 2-wire bus 1'h0 0xd730 reg_top_lock1out 0 rw lock1 direct output tpsd/mepg_lock enable 1'h0 reg_top_lock1_tpsd 1 rw lock1 output, 1: tpsd_lock, 0: mpeg_lock 1'h0 reg_top_lock2out 2 rw lock2 direct output tpsd/mepg_lock enable 1'h0 reg_top_lock2_tpsd 3 rw lock2 output, 1: tpsd_lock, 0: mpeg_lock 1'h0 reg_top_lock3out 4 rw lock3 direct output tpsd/mepg_lock enable 1'h0 reg_top_lock3_tpsd 5 rw lock3 output, 1: tpsd_lock, 0: mpeg_lock 1'h0 reg_top_lock4out 6 rw lock4 direct output tpsd/mepg_lock enable 1'h0 reg_top_lock4_tpsd 7 rw lock4 output, 1: tpsd_lock, 0: mpeg_lock 1'h0 0xd731 reg_top_pwrdw_hwen 0 rw shut down clock without interrupting control u nit. 1'h0 reg_top_pwrdw 6 rw turn on pwrdw function 1'h0 www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 45 reg_top_pwrdw_inv 7 rw turn on pwrdw inverse function 1'h0 0xd734 reg_top_lock1on 0 rw gpio on 1'h0 reg_top_lock1en 1 rw gpio on 1'h0 reg_top_lock1o 2 rw gpio on 1'h0 reg_top_lock1i 3 rs gpio on 1'h0 reg_top_lock2on 4 rw gpio on 1'h0 reg_top_lock2en 5 rw gpio on 1'h0 reg_top_lock2o 6 rw gpio on 1'h0 reg_top_lock2i 7 rs gpio on 1'h0 0xd735 reg_top_gpio0on 0 rw gpio output 1'h1 reg_top_gpio0en 1 rw gpio output 1'h1 reg_top_gpio0o 2 rw gpio output 1'h0 reg_top_gpio0i 3 rs gpio output 1'h0 reg_top_gpio1on 4 rw gpio output 1'h1 reg_top_gpio1en 5 rw gpio output 1'h1 reg_top_gpio1o 6 rw gpio output 1'h1 reg_top_gpio1i 7 rs gpio output 1'h0 0xd736 reg_top_gpio2on 0 rw gpio output 1'h0 reg_top_gpio2en 1 rw gpio output 1'h0 reg_top_gpio2o 2 rw gpio output 1'h0 reg_top_gpio2i 3 rs gpio output 1'h0 reg_top_gpio3on 4 rw gpio output 1'h0 reg_top_gpio3en 5 rw gpio output 1'h0 reg_top_gpio3o 6 rw gpio output 1'h0 reg_top_gpio3i 7 rs gpio output 1'h0 0xd737 reg_top_gpio4on 0 rw gpio output 1'h0 reg_top_gpio4en 1 rw gpio output 1'h0 reg_top_gpio4o 2 rw gpio output 1'h0 reg_top_gpio4i 3 rs gpio output 1'h0 0xd73b reg_afe_mem1[3] 3 rws 1: adc input range is 2v peak-to-peak 0: adc input range is 1v peak-to-peak 1'h0 0xd740 reg_top_padmpdr2 0 rw pads driving strength 1'h0 www.datasheet.co.kr datasheet pdf - http://www..net/
afa technologies confidential proprietary 46 reg_top_padmpdr4 1 rw pads driving strength 1'h1 reg_top_padmpdr8 2 rw pads driving strength 1'h0 reg_top_padmpdrsr 3 rw pads driving strength 1'h0 0xd742 reg_rst_i2cs 0 rw reset of 2-wire slave 1'h0 reg_rst_i2cm 1 rw reset of 2-wire master 1'h0 0xd743 reg_top_gpiosdaon 0 rw gpio output 1'h0 reg_top_gpiosdaen 1 rw gpio output 1'h0 reg_top_gpiosdao 2 rw gpio output 1'h1 reg_top_gpiosdai 3 rs gpio output 1'h0 reg_top_gpiosclon 4 rw gpio output 1'h0 reg_top_gpiosclen 5 rw gpio output 1'h0 reg_top_gpiosclo 6 rw gpio output 1'h1 reg_top_gpioscli 7 rs gpio output 1'h0 www.datasheet.co.kr datasheet pdf - http://www..net/

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